A scan line conversion circuit is used, particularly in display devices such as liquid crystal displays or plasma displays, for converting input video signals to the number of scan lines in the display device.
In the scan line conversion circuit, in general, when an interlace signal has been input, the number of scan lines is converted by a method wherein, independently of whether the input signal is a static image or a moving image, the scan line is interpolated within the field and, in addition, is converted to a non-interlace signal, or by a method wherein, after conversion to a non-interlace signal by three-dimensional motion adaptive scan line interpolation is once performed, the number of scan lines is converted by resolution conversion processing (Japanese Patent Laid-Open No. 253365/2000).
FIG. 1 is a block diagram showing the construction of a conventional system, FIG. 2 a circuit diagram showing a conventional three-dimensional motion adaptive sequential scan conversion circuit, and FIG. 3 a circuit diagram showing a conventional scan line conversion circuit. As shown in FIG. 1, a video signal is input through an input terminal 301 into a three-dimensional motion adaptive sequential scan conversion circuit 302, is converted to a non-interlace signal by three-dimensional motion adaptive sequential scan conversion, and is then input into a resolution conversion circuit 304 where the interlace signal is converted to the resolution of the display device. Thus, when the three-dimensional motion adaptive sequential scan conversion is used in combination with the resolution conversion, after the three-dimensional motion adaptive sequential scan conversion is performed as shown in FIG. 2, the resolution conversion is performed as shown in FIG. 3. In this case, as shown in FIG. 1, SDRAM 303 for sequential scan conversion should be provided separately from SDRAM 305 for resolution conversion.
In the conventional three-dimensional motion adaptive sequential scan conversion circuit 302 shown in FIG. 2, the interlace signal input into the signal terminal 1 is supplied to a field memory 3, a motion detector 6, and an adder 5. Further, the output of the field memory 3 is input into a next-stage field memory 4.
The signal output from the field memory 4 is input into the adder 5 and is further input into a multiplier 12 for multiplying the signal, output from the adder 5, by ½. In the adder 5 and the multiplier 12, a signal not sent to the current field due to the interlace signal is generated from a signal of one field before the contemplated signal and a signal of one field after the contemplated signal, and interpolation processing, in the case where the input signal is a static image, is performed.
The signal output from the field memory 3 is sent to a 1H delay memory 8, an adder 10, and a multiplier 13, for one-line delaying. The signal output from the 1H delay memory 8 is sent to the adder 10. Further, the output of the adder 10 is sent to a multiplier 13 for multiplying the output signal by ½.
In the adder 10, in the input interlace signal, the upper scan line is added to the lower scan line. Therefore, a signal not to sent to the current field is generated from the upper and lower scan lines, and interpolation processing, in the case where the input signal is a moving image, is performed.
On the other hand, in the motion detector 6, the signal from the input terminal 1 and a signal, which has been delayed by two fields by the field memories 3, 4, that is, a one-frame-before signal, are input, and the motion level is detected by determining the difference between these signals. In the motion detector 6, processing is performed to transform the motion quantity into a coefficient from the motion level. The coefficient output from the motion detector 6 is sent to multipliers 19, 20 where the mixing ratio of the signal, which has been interpolated for the static image, to the signal, which has been interpolated for the moving image, is adaptively varied according to the motion quantity of the input signal.
The output of the multipliers 19 is added to the output of the multiplier 20 in an adder 21, followed by sending from the adder 21 to a line memory 102. Further, the output of the field memory 3 is input into a line memory 101. An output is selected by a switch 103 from the output of the line memory 101 and the output of the line memory 102, and the selected output is sent to a scan line conversion circuit 304.
The conventional scan line conversion circuit 304 shown in FIG. 3 comprises: an FIFO (first in first out) memory 207 for scan line conversion; an address generator 205 for generating an address; a memory control unit 202 for controlling the memory; a coefficient generator 206 for generating a coefficient from a signal obtained from the address generator 205; multipliers 211 to 214 for successively multiplying signals, produced by the scan conversion processing, by the coefficient; and an adder 215 for adding the outputs of the multipliers 211 to 214 together. The signal output from the FIFO memory 207 is sent to a 1H delay memory 208 for one-line delaying and a multiplier 214. The signal output from the 1H delay memory 208 is sent to a 1H delay memory 209 and an adder 213 which have been provided in tandem. The signal output from the 1H delay memory 209 is sent to a 1H delay memory 210 and an adder 212. The signal output from the 1H delay memory 210 is sent to the adder 211.
In the address generator 205, a spatial position after scan line interpolation necessary for scan line conversion, that is, an address, is generated from a synchronous signal of the signal input into a terminal 204 and an enlargement ratio, which is input into a terminal 203 and sets the enlargement ratio in the vertical direction. Based on the address output from the address generator 205, the memory control unit 202 decides a line to be used for resolution conversion. That is, the memory control unit 202 generates a memory control signal for the read/write control of the FIFO memory 207 and the one-line delay memories 208, 209, 210 so as to send line data necessary for resolution conversion to the multipliers 211 to 214 provided in the final stage. Further, in the coefficient generator 206, a coefficient to be sent to the multipliers 211 to 214 is generated based on the signal output from the address generator 205.
Signals equivalent to sequentially scan converted signals are input into the multipliers 211 to 214, and, in the multipliers 211 to 214, the signals are multiplied by the coefficient sent from the coefficient generator 206, and the obtained values are added together in the adder 215, whereby scan line conversion can be performed.
Japanese Patent Laid-Open No. 253365/2000 further proposes a scan line conversion circuit comprising conventional three-dimensional scan line interpolation circuit and resolution conversion circuit.
Resolution conversion circuits are classified into two types. In one type, a frame memory using DRAM is provided. In the other type, no frame memory is provided, and a line memory for several lines is provided within LSI. The provision of the frame memory is advantageous in that the conversion of a field frequency can be carried out or in that partial enlargement or reduction is possible.
Further, at the present time, in many cases, three-dimensional motion adaptive sequential scan conversion is not carried out, and, instead, at the time of resolution conversion processing in the vertical direction, offsetting the initial value for each field serves also as sequential scan conversion. In this case, however, the interlace signal is subjected to intra-field interpolation for sequential scan conversion. Also in the static image, line flicker occurs. Accordingly, the adoption of a method, wherein, in order to prevent the line flicker, resolution conversion is performed after three-dimensional motion adaptive sequential scan conversion, would be led to improved image quality.
When scan line interpolation is performed only within the field, the circuit scale may be small. In this case, however, the line flicker disadvantageously occurs also in the static image. On the other hand, conversion to an interlace signal by three-dimensional motion adaptive scan line interpolation followed by scan line interpolation by resolution conversion poses problems such as large circuit scale, high cost, and required large mounting area.
Further, as shown in FIG. 1, SDRAM 303 for sequential scan conversion should be provided separately from SDRAM 305 for resolution conversion. This poses a problem of the necessity of increasing the number of external SDRAMs. Furthermore, when the scan line conversion circuit disclosed in Japanese Patent Laid-Open No. 253365/2000 has a frame memory, the frame memory should be provided in the three-dimensional scan line interpolation and the resolution conversion circuit. As with the conventional technique, disadvantageously, the number of external SDRAMs should be increased.
Further, in the conventional circuit, when an HDTV signal is input into a display device wherein the number of scan lines is, for example, 768, a method should be used wherein, after a digital HDTV signal input at a clock rate of 74.25 MHz is converted by three-dimensional motion adaptive sequential scan conversion to a signal of the number of scan lines 1080 and clock rate 148.5 MHz, the number of scan lines is converted to 768. In this case, in the course of signal processing, operation should be performed at a higher frequency than the clock rate required for resolution in the display device.
Further, in recent years, an increase in size of liquid crystal displays or the development of large-screen plasma displays has led to a trend toward the practical use of large-screen televisions. In these large-screen televisions, there is a strong demand for an improvement in image quality in the case of the input of interlace signals, and, in addition, a reduction in cost is indispensable. Therefore, the development of a scan line conversion circuit satisfying these demands has been desired in the art.